MCS -12 QUESTION & ANSWER June -2023

May 06, 2024

MCS -12 QUESTION & ANSWER June -2023

(a) Describe the structure of the 8086 micro-processor with the help of a diagram. 6

Structure of 8086 Microprocessor

The 8086 microprocessor, a 16-bit processor developed by Intel, features a complex architecture comprising various functional units. Here's a brief overview:

1. Arithmetic and Logic Unit (ALU): Responsible for performing arithmetic and logical operations.
2. Control Unit (CU): Coordinates activities of all other units, fetching instructions, and decoding them.
3. Registers: Includes general-purpose registers (AX, BX, CX, DX), segment registers (CS, DS, SS, ES), and index registers (SI, DI, BP, SP).
4. Instruction Queue: Holds instructions fetched from memory.
5. Bus Interface Unit (BIU): Manages communication with the external memory and peripherals.
6. Execution Unit (EU): Executes instructions fetched by the BIU.
7. Segmentation and Addressing: Utilizes segment registers and pointers for memory addressing.
8. Interrupt Controller: Manages interrupts from external devices.

These components work together to execute instructions and handle data within the 8086 microprocessor.

https://youtu.be/DLrrcm2SUTQ?si=R-kfKFgFoUEzITFT

https://youtu.be/nV0pC0-zJc0?si=DKCZzkqSnCNRAqe3

(b) What is an instruction cycle? Explain with the help of a flowchart. 6

Instruction Cycle

The instruction cycle, also known as the fetch-decode-execute cycle, is the fundamental process by which a computer executes instructions. It consists of several steps:

1. Fetch: The processor fetches the next instruction from memory into its instruction register (IR).

2. Decode: The fetched instruction is decoded to determine what operation it represents and the operands involved.

3. Execute : The decoded instruction is executed, which may involve performing arithmetic/logic operations, accessing data from memory, or controlling I/O devices.

4. Update: Any necessary updates to the program counter (PC) or other registers occur to prepare for the next instruction.

Here's a simplified flowchart illustrating the instruction cycle:

Start

Fetch Instruction

Decode

Execute

Update PC/Register

Repeat

This cycle continues until the program completes or encounters a branch or jump instruction.

(i) 1010.0001

(ii) -0.0000111

Representing Numbers in IEEE-754 Single Precision Format

(i) Positive Number: 1010.0001

To represent \(1010.0001\) in IEEE-754 single precision format:

1. Sign bit: Since it's positive, sign bit is \(0\).
2. Exponent: \(1010.0001\) can be expressed as \(1.0100001 \times 2^3\). So, exponent is \(3 + 127 = 130\) which in binary is \(10000010\).
3. Mantissa: The mantissa is \(01000010000000000000000\) (the fraction part of the binary representation).

So, the IEEE-754 representation of \(1010.0001\) is:

\[ 0 \ 10000010 \ 01000010000000000000000 \]

(ii) Negative Number: -0.0000111

To represent \(-0.0000111\) in IEEE-754 single precision format:

1. Sign bit: Since it's negative, sign bit is \(1\).
2. Exponent: \(0.0000111\) can be expressed as \(1.11 \times 2^{-4}\). So, exponent is \(4 + 127 = 131\) which in binary is \(10000011\).
3. Mantissa: The mantissa is \(11000000000000000000000\) (the fraction part of the binary representation).

So, the IEEE-754 representation of \(-0.0000111\) is:

\[ 1 \ 10000011 \ 11000000000000000000000 \]

These representations follow the IEEE-754 single precision format.

https://youtu.be/T_Wxrp-2DZQ?si=Wx5Mk1U1i2puE5-f

https://youtu.be/8afbTaA-gOQ?si=15-8DJSp08DGruEu

https://youtu.be/9lLpAFapndo?si=BDP8FWFn35UVJdP5

(d) Explain instruction pipeline with the help of a diagram. 4

https://youtu.be/nv0yAm5gc-E?si=2N2IB3mFjTaLxHom

(e) What are the different kinds of Interrupts? How does CPU know that an interrupt has occurred? 5

Types of Interrupts and Detection

1. Hardware Interrupts: Generated by external devices like I/O operations or internal hardware issues.
2. Software Interrupts: Initiated by software requests such as system calls or error conditions.
3. External Interrupts: Triggered by peripherals like keyboards, mice, or network interfaces.
4. Internal Interrupts: Generated internally by the CPU, like timer interrupts for multitasking.

Interrupt Detection:

The CPU identifies interrupts through interrupt lines connected to an interrupt controller. When an external device or internal process requires attention, it sends an interrupt request. The interrupt controller prioritizes and forwards these requests to the CPU. The CPU then suspends its current task, saves its state, and jumps to the corresponding Interrupt Service Routine (ISR) based on a predetermined mapping. The ISR handles the interrupt, and once done, the CPU resumes its previous task.

https://youtu.be/1aG3aFEKxyA?si=F0WIJlWVk9iZAwUe

(f) What is DMA ? Explain the functions of DMA. 5

DMA (Direct Memory Access)

DMA is a computer architecture feature that enables peripheral devices to transfer data directly to or from the system's memory without involving the CPU.

Functions of DMA:

1. Data Transfer: DMA facilitates high-speed data transfers between peripheral devices and memory, enhancing system performance.

2. Offloading CPU: By bypassing the CPU for data transfer tasks, DMA reduces CPU overhead, allowing it to focus on executing other tasks.

3. Asynchronous Operations: DMA enables asynchronous data transfers, allowing the CPU to continue processing other tasks while data transfer occurs in the background.

4. Efficient I/O Operations: DMA enhances the efficiency of Input/Output (I/O) operations by eliminating the need for CPU intervention during data transfer.

5. Resource Sharing: DMA enables multiple devices to share system memory efficiently, optimizing resource utilization.

https://youtu.be/kq30OAb6Ni0?si=buFYvlS3NHqwHmzF

(g) Consider a four variable Boolean function :

\[\mathrm{F}=\Sigma(0,4,6,7,8,10,11,15)\]

Minimize this function using K-map and draw the resultant function using logic gates.

https://youtu.be/3HmVJaSEzhg?si=E8Hr0FWxsuN7dEK0 6

(h) Convert decimal number (49.25)10 into: 4
(i) binary
(ii) hexadecimal
(iii) octal

(i) Binary:

To convert the integer part (49) into binary, we repeatedly divide by 2 and note the remainders until the quotient becomes zero.
49 ÷ 2 = 24 remainder 1
24 ÷ 2 = 12 remainder 0
12 ÷ 2 = 6 remainder 0
6 ÷ 2 = 3 remainder 0
3 ÷ 2 = 1 remainder 1
1 ÷ 2 = 0 remainder 1

Reading the remainders from bottom to top, we get: 110001.

Now, for the fractional part (0.25), we repeatedly multiply by 2 and take the integer part.
0.25 × 2 = 0.5 → 0
0.5 × 2 = 1.0 → 1

So, the binary representation of 0.25 is 0.01.

Combining the integer and fractional parts, we get 49.25 as 110001.01 in binary.

(ii) Hexadecimal:
To convert 49 to hexadecimal, we divide by 16.
49 ÷ 16 = 3 remainder 1 (3 in hexadecimal is 3)
3 ÷ 16 = 0 remainder 3 (1 in hexadecimal is 1)

So, the integer part of 49 in hexadecimal is 31.

Now, for the fractional part (0.25), we can multiply by 16 and take the integer part.
0.25 × 16 = 4.0 → 4 (4 in hexadecimal is 4)

So, the fractional part of 0.25 in hexadecimal is 4.

Combining them, we get 49.25 as 31.4 in hexadecimal.

(iii) Octal:
To convert 49 to octal, we divide by 8.
49 ÷ 8 = 6 remainder 1
6 ÷ 8 = 0 remainder 6

So, the integer part of 49 in octal is 61.

Now, for the fractional part (0.25), we can multiply by 8 and take the integer part.
0.25 × 8 = 2.0 → 2

So, the fractional part of 0.25 in octal is 2.

Combining them, we get 49.25 as 61.2 in octal.

2. (a) Explain the differences between microprogrammed control and hardwired control. 5

**Microprogrammed Control vs. Hardwired Control**

**Microprogrammed Control:**

In microprogrammed control, control signals are generated by a microprogram stored in memory. This microprogram consists of a sequence of microinstructions, each controlling a specific operation. Altering the control behavior involves modifying the microinstructions, providing flexibility. However, it requires additional memory and incurs overhead due to the instruction fetch cycle.

**Hardwired Control:**

Hardwired control uses fixed logic circuits to generate control signals directly. The control logic is implemented using combinational and sequential logic gates. It offers faster execution since there's no need for instruction decoding, but it lacks flexibility as any changes require modifying the hardware directly. It's more suitable for simple and repetitive tasks. However, it can be complex to design and modify.

(b) Draw and explain the logic diagram of a \( 3 \times 8 \) decoder.5

A \( 3 \times 8 \) decoder takes in a 3-bit input and selects one of eight outputs based on the input combination. Each output corresponds to a unique combination of the three input bits. Here's a simple explanation along with a logic diagram:

Logic Diagram:

```

___

A0 --| |--- O0

| D |--- O1

A1 --| e |--- O2

| c |--- O3

A2 --| o |--- O4

| d |--- O5

| e |--- O6

| r |--- O7

---

```

Explanation:

- A0, A1, and A2 are the 3 input lines.

- O0 through O7 are the 8 output lines.

- Each output line is connected to an AND gate.

- The AND gate for each output is connected to one of the input lines. The connection pattern ensures that each output corresponds to a unique combination of the input lines.

- When an input combination appears, the corresponding output line goes high (logic 1), while all other output lines stay low (logic 0).

https://youtu.be/RdnGQ-E-YgE?si=OZqs0A1pX1iIaBO0

(c) Design a combinational circuit with three inputs \( x, y, z \) and three outputs A, B, C. When the binary equivalent of input to this circuit is \( 0,1,2 \) or 3 the binary output is one greater than the input. When the binary equivalent of input is \( 4,5,6 \) or 7 the binary output is one less than the input. Also draw the truth table.

To design the combinational circuit, we can use logic gates to implement the desired behavior based on the given conditions. Let's break down the problem:

1. When the input is in the range `\(0\)` to `\(3\)`, the output is one greater than the input.

2. When the input is in the range \(4\) to \(7\), the output is one less than the input.

We'll design a circuit using AND, OR, and NOT gates to achieve this. Let's denote the inputs as \(x\), \(y\), and \(z\), and the outputs as \(A\), \(B\), and \(C\).

Here's the truth table:

Now, let's design the circuit based on this truth table:

- `\(A = \overline{x} \cdot \overline{y} \cdot \overline{z} + \overline{x} \cdot y \cdot z\)`

-` \(B = \overline{x} \cdot y \cdot \overline{z} + x \cdot \overline{y} \cdot z + x \cdot y \cdot \overline{z}\)`

-` \(C = x \cdot \overline{y} \cdot \overline{z} + x \cdot y \cdot z\)`

This circuit will give the desired outputs based on the given conditions.

https://youtu.be/nBM3xeq9DxY?si=pWqFFvhZma8WEJl6

(d) Find the 9's and 10's complement of 128. Then convert 128 to binary and find 1's and 2's complement.

To find the 9's complement of a number, you subtract each digit from 9. Similarly, to find the 10's complement, you subtract each digit from 10.

Let's start with the number 128:

1. **9's Complement:**
\(9 - 1 = 8\)
\(9 - 2 = 7\)
\(9 - 8 = 1\)

So, the 9's complement of 128 is 871.

2. **10's Complement:**
\(10 - 1 = 9\)
\(10 - 2 = 8\)
\(10 - 8 = 2\)

So, the 10's complement of 128 is 872.

Now, let's convert 128 to binary:

\(128_{10} = 10000000_2\)

1. **1's Complement:** To get the 1's complement, you simply flip all the bits.

\(10000000_2\) becomes \(01111111_2\).

2. **2's Complement:** To get the 2's complement, you add 1 to the 1's complement.

\(01111111_2 + 1 = 10000000_2\)

So, the 1's complement of 128 is \(01111111_2\) and the 2's complement is \(10000000_2\).

https://youtu.be/pXIfEklKsOQ?si=cTcT038KkzQX8OD5

https://youtu.be/nKzy4s4sI-4?si=-eBaDjjr6omXlu4u

3(a) Add 25 and ( -25 ) in binary using 8 -bit register for the following representations :

(i) Signed magnitude representation

(ii) Signed 1's complement

(iii) Singed 2's complement

Adding 25 and (-25) in binary using an 8-bit register involves understanding signed magnitude, one's complement, and two's complement representations.

Signed Magnitude Representation:
25 in binary: 00011001
-25 in binary (Sign-Magnitude): 10011001

Adding these directly:
00011001
+10011001
----------
10110010

The result exceeds 8 bits, so it overflows. We lose the most significant bit, yielding: 0110010, which is 50 in decimal.

One's Complement Representation:
25 in binary: 00011001
-25 in binary (One's Complement): 11100110

Adding:
00011001
+11100110
----------
11111111

Here, we have a carry, resulting in 1 with an overflow. The true answer is 0. The most significant bit, 1, indicates a negative result.

Two's Complement Representation:
25 in binary: 00011001
-25 in binary (Two's Complement): 11100111

Adding:
00011001
+11100111
----------
00000000

The result is 0, which is accurate. The overflow is discarded. The most significant bit being 0 indicates a positive result.

(b) Explain the following instructions of 8086 assembly language with the help of an example :

(i) \( \mathrm{ADC} \)

(ii) MUL

(iii) \( \mathrm{XOR} \)

(iv) \( \mathrm{ROL} \)

(i) ADC (Add with Carry):

ADC (Add with Carry) is an instruction in 8086 assembly language that adds two operands along with the value of the carry flag and stores the result in the destination operand. This instruction is useful for multi-byte addition operations where the carry from a previous operation needs to be considered.

MOV AX, 1000h ; Load AX with 1000h

MOV BX, 2000h ; Load BX with 2000h

CLC ; Clear carry flag

ADC AX, BX ; Add BX to AX with carry

In this example, if the carry flag is clear, ADC will add AX and BX directly. If the carry flag is set, ADC will add AX, BX, and 1 (carry flag) together.

(ii) MUL (Multiply):

MUL (Multiply) is an instruction in 8086 assembly language used for unsigned multiplication. It multiplies an 8 or 16-bit operand by the contents of the AX register, producing a double-length result stored in DX:AX (for 16-bit operands) or AX alone (for 8-bit operands).

MOV AL, 10 ; Load AL with 10

MOV BL, 20 ; Load BL with 20

MUL BL ; Multiply AL by BL

After execution, AX will contain the low 16 bits of the result (200), and DX will contain the high 16 bits (0).

(iii) XOR (Exclusive OR):

XOR (Exclusive OR) is an instruction in 8086 assembly language used for bitwise exclusive OR operation. It performs the XOR operation between two operands and stores the result in the destination operand.

MOV AX, 1000h ; Load AX with 1000h

MOV BX, 2000h ; Load BX with 2000h

XOR AX, BX ; Perform XOR between AX and BX

After execution, AX will contain the low 16 bits of the result (200), and DX will contain the high 16 bits (0).

(iv) ROL (Rotate Left):

ROL (Rotate Left) is an instruction in 8086 assembly language that rotates the bits of the operand to the left. The carry flag is shifted into the least significant bit, and the most significant bit is shifted into the carry flag.

Example:

MOV AX, 1000h ; Load AX with 1000h

ROL AX, 1 ; Rotate AX left by 1 bit

After execution, AX will contain the value of 2000h, as the bit that was originally in the most significant position has been shifted into the carry flag, and the carry flag has been shifted into the least significant position.

(c) Explain the role of Interrupt Vector Table (IVT) in the context of 8086 microprocessor with the help of a diagram.

The Interrupt Vector Table (IVT) in the 8086 microprocessor is a data structure that stores addresses of interrupt handlers.

It consists of 256 entries, each corresponding to a specific interrupt or exception.

When an interrupt occurs, the processor looks up the corresponding entry in the IVT to find the address of the interrupt service routine (ISR).

The ISR is then executed to handle the interrupt, which may involve saving the state of the current process, executing the appropriate code to handle the interrupt, and then restoring the previous state.

The IVT provides a mechanism for managing and responding to interrupts in a structured and efficient manner.

Below is a simplified diagram illustrating the structure of the Interrupt Vector Table:

4. (a) The following memory units are specified by the number of words times the number of bits per word. How many address lines and input-output data lines are needed in each case ?

(i) \( 2 \mathrm{~K} \times 16 \)

(ii) \( 64 \mathrm{~K} \times 8 \)

- For \(2 \mathrm{~K} \times 16\):

- Address lines needed: \( A = \log_2(2 \mathrm{~K}) = \log_2(2048) = 11 \) address lines.

- Input-output data lines needed: \( D = 16 \) bits per word.

- For \(64 \mathrm{~K} \times 8\):

- Address lines needed: \( A = \log_2(64 \mathrm{~K}) = \log_2(65536) = 16 \) address lines.

- Input-output data lines needed: \( D = 8 \) bits per word.

(b) What is a micro-operation ? Explain the sequence of micro-operations required to fetch an instruction stored in the memory in the context of a Von Neumann machine.

A micro-operation is a basic operation performed by a CPU, such as reading from or writing to registers, performing arithmetic or logic operations, or controlling data flow.

In a Von Neumann machine, fetching an instruction from memory typically involves several micro-operations. First, the CPU sends the address of the instruction to the memory unit. Then, the memory unit retrieves the instruction from the specified address and transfers it to the CPU. Meanwhile, the CPU decodes the instruction and prepares for its execution. Finally, the CPU proceeds to execute the fetched instruction according to its opcode and operands. This sequence of micro-operations allows the CPU to effectively retrieve, interpret, and execute instructions stored in memory.

(i) Register addressing

(ii) Index addressing

(iii) Direct addressing

(i) Register addressing involves specifying a register as the operand in an instruction. For example, in the instruction "ADD R1, R2", the values in registers R1 and R2 are added together. This mode is efficient for operations involving data already stored in registers, reducing memory accesses and enhancing speed.

(ii) Index addressing involves adding an offset value to a base register to calculate the effective address. For instance, in the instruction "LOAD R1, (R2 + 10)", the contents of the memory location at the address stored in register R2 plus 10 are loaded into register R1. This mode facilitates accessing elements in arrays or data structures.

(iii) Direct addressing involves specifying the memory address directly in the instruction. For example, in the instruction "LOAD R1, 2000", the contents of memory address 2000 are loaded into register R1. This mode is straightforward but may limit flexibility in programming.

(d) Find the even and odd parity bits for the following 7 -bit data : 4

(i) 1010101

(ii) 0000111

For a 7-bit data with parity bits, we typically use one parity bit to ensure even parity and another for odd parity.

(i) For the 7-bit data "1010101":

Even Parity: The number of 1s in the data is 4, which is even. So, the even parity bit is 0.
Odd Parity: The number of 1s is already odd, so the odd parity bit is 1.
So, the even parity bit is 0 and the odd parity bit is 1.

(ii) For the 7-bit data "0000111":

Even Parity: The number of 1s in the data is 3, which is odd. So, the even parity bit is 1.
Odd Parity: The number of 1s is already odd, so the odd parity bit is 1.
So, the even parity bit is 1 and the odd parity bit is 1.

In summary:
(i) Even parity bit: 0, Odd parity bit: 1
(ii) Even parity bit: 1, Odd parity bit: 1

5. (a) Explain the terms ASCII and UNICODE. 3

ASCII (American Standard Code for Information Interchange):

Character encoding standard representing text in computers and other devices.
Uses 7 bits to represent 128 characters, including letters, numbers, punctuation, and control characters.
Developed in the 1960s, widely used in early computer systems and communication protocols.

UNICODE:

Universal character encoding standard supporting multiple languages and scripts.
Uses variable-width encoding, allowing representation of over a million characters.
Includes characters from various writing systems, emojis, symbols, and more.
Addresses limitations of ASCII by providing a unified encoding system for global text interchange.

(b) Register 'A' holds 8-bit binary 11011001. Determine \( B \) operand and the logic microoperation to be performed in order to change the value in \( \mathrm{A} \) to :
6
(i) 00001001
(ii) 11111001
(iii) 00100110

Solution :

To change the value in register A to the specified values:

(i) To transform A to 00001001, B should contain the binary value 11010000, and the logic microoperation to be performed is an AND operation.

(ii) For A to become 11111001, set B to 00100000, and perform a logical OR operation between A and B.

(iii) To convert A to 00100110, assign B the binary value 11111111, and execute a logical AND operation between A and B.

In summary:
(i) B = 11010000, Logic microoperation = AND
(ii) B = 00100000, Logic microoperation = OR
(iii) B = 11111111, Logic microoperation = AND

(c) Write the assembly language code using 8086 assembly language for performing the following operation :
6
`\[\mathrm{Z}=((\mathrm{A}-\mathrm{B}) / 10 * \mathrm{C}) * * 2\]`

Solution:

DATA SEGMENT
A DW ?
B DW ?
C DW ?
Z DW ?
DATA ENDS

CODE SEGMENT
START:
MOV AX, @DATA
MOV DS, AX

; Read values of A, B, and C
MOV AH, 01H
INT 21H ; Input A
SUB AL, '0' ; Convert ASCII to binary
MOV A, AL

MOV AH, 01H
INT 21H ; Input B
SUB AL, '0' ; Convert ASCII to binary
MOV B, AL

MOV AH, 01H
INT 21H ; Input C
SUB AL, '0' ; Convert ASCII to binary
MOV C, AL

; Subtract B from A
MOV AX, A
SUB AX, B
MOV DX, 0 ; Clear DX for division
MOV BX, 10 ; Divisor for division
DIV BX ; AX = AX / BX, quotient in AX, remainder in DX

; Divide result by 10
MOV BX, 10
DIV BX ; AX = AX / BX, quotient in AX, remainder in DX

; Multiply result by C
MOV BX, C
MUL BX ; AX = AX * BX

; Multiply result by 2
SHL AX, 1 ; AX = AX * 2

; Store result in Z
MOV Z, AX

; Display result
MOV AH, 02H
MOV DL, Z
ADD DL, '0' ; Convert binary to ASCII
INT 21H

MOV AH, 4CH ; Exit program
INT 21H

CODE ENDS
END START

(d) Explain the use of circular overlapped register window in a RISC processors with the help of a diagram.

- Circular overlapped register windows in RISC processors optimize register usage during function calls by organizing registers into sets, typically including a local and global set.
- When a function is called, the local set becomes active, while the previous window becomes the global set, preserving its contents.
- Parameters and local variables are stored in the local set, ensuring fast access without needing to access memory.
- As function calls nest, new windows are created, and the active window shifts in a circular manner, reusing registers from previous windows.
- This circular shifting minimizes the need for memory access to spill and reload registers, enhancing performance by reducing latency.
- Diagrams often illustrate this cyclic movement of windows, demonstrating how registers are reused and maintained across function calls.